Systems and methods herein generally relate to processing images and more particularly to rendering images to lower bits per pixel formats using reduced numbers of registers.
In systems that convert higher-bit size image data to reduced-bit size image data (so as to allow the image data to be more easily processed) a higher-bit pixel is compared to a threshold value (or threshold values) and, depending upon the relationship of the value of the higher-bit pixel, a reduced bit size data value is generated. For example, if the possible pixel value of the higher-bit image data has a value between 0 and 255, the threshold value may be 128. A pixel value of the higher-bit image data that is equal to or greater than 128 would generate a binary value of 1 (representing a gray scale value of 255) and a pixel value of the higher-bit image data that is equal to or less than 128 would generate a binary value of 0 (representing a gray scale value of 0). In each instance, there would be a difference between the original higher-bit pixel and the converted value, and this difference is referred to as the “error” of the conversion process.
In a conversion process that utilizes error diffusion, this error can be diffused (scattered or propagated) to neighboring pixels. In some systems, the error may be conventionally propagated to the next pixel in the scanline and to adjacent pixels in the next scanline. Moreover, in error diffusion processes, the error is weighted such that an adjacent pixel does not necessarily receive all the error, but only a portion thereof.
Such error diffusion is used in many of today's digital imaging products to render higher-bit contone images to a print-ready lower-bit format. The wide acceptance of error diffusion is mainly due to the inherent rendering properties, which provide favorable print image quality without generating artifacts (i.e. moire’, etc.). Moreover, error diffusion provides a good compromise when processing documents with “mixed” content, since it faithfully preserves the image density of photographs, while at the same time rendering text, line-art, and graphics with acceptable print quality.
One drawback of error diffusion, however, is the computational cost of processing images for high-speed applications due to the serial nature of the algorithm. The error diffusion processing node is usually the system-level bottleneck. This is especially true in a software image-path (SWIP) environment (as opposed to the traditional hardware-based FPGA/ASIC devices), where developing high-speed (software-based) image-processing nodes is used to providing a flexible and viable solution.
Various multi-threaded and data parallel techniques accelerate the overall processing speed of images processed via error diffusion. For example, images can be partitioned and sequentially processed via error diffusion one raster or scanline at a time using several concurrent threads in a time-multiplexed fashion, but this requires careful scheduling of the start of each raster relative to the other, to eliminate inter-scanline boundary artifacts. Likewise, other techniques attempt to apply data parallelism on a “tile-to-tile” or “inter-raster” basis in order to improve the overall throughput rate, but these solutions tend to produce low-frequency image artifacts around the periphery of the segmented borders due to the inability to properly distribute the error from one image segment to the next.